4/96 - Present    

                         MicroVision, Inc - Self-Employed

                         6 Widgeon Drive

                         Sheridan, Wyoming 82801

In the past thirteen years I have provided support for companies seeking experience in integrated circuit layout and verification. I have extensive experience creating compact full custom layouts using a broad variety of different semiconductor processes. My projects have included building low voltage and high voltage analog circuits, custom and semi-custom digital circuits, writing verification decks for Cadence and Tanner tools, and building photo test reticles. I have experience with Cadence Tools, Tanner Tools, Silvaco Tools and Mentor Calibre software and have completed approximately 200 chips and circuits in my 25-year career.

      4/93 - 4/96       

                         American Microsystems, Inc.

                         Pocatello, Idaho

                         Design Specialist - Research & Design

My main responsibility was to provide physical design support for process integration and development.  Tasks include construction of test chips, scribe/frame/alignment structures, writing verification (DRC, ERC, LPE, LVS), and managing AMI's reticle information database. I interfaced with Manufacturing, Photo and Engineering on a daily basis.

      4/91 - 4/93       

                         United Technologies Microelectronics

                         Colorado Springs, Colorado

                         Circuit Designer I

Job function entailed physical design and verification of CMOS integrated circuits.  I was involved with the construction of over twenty circuits and macro cells.  Other activities include layout and development of devices in new processes, supporting UTMC foundry and compiled design activities.  

      6/84 - 4/91       

                         NCR Microelectronics Division

                         Fort Collins, Colorado

                         Design Tech III

Responsibilities included physical design and verification of CMOS integrated circuits.  Completed over eighty circuit/chip layouts with responsibilities consisting of schematic capture, timing analysis, auto place and route, prototyping, testing and characterization of CMOS digital and analog circuits.